IP Design Engineer

자격 요건 · 4개

• 3+ years of experience in RTL design using SystemVerilog or Verilog
• Proven experience spanning from initial architecture definition to final RTL implementation
• Proficiency in logic simulation tools (VCS, Xcelium) with the ability to resolve complex RTL issues
• experience with industry-standard quality flows, including Lint, CDC, DFT, and Synthesis

우대 사항 · 4개

• Experience in designing specialized Arithmetic (Floating-Point) units and optimized buffer structures
• Deep understanding of MMU architectures and experience utilizing ARM MMU in IP design
• Strong understanding of AMBA-BUS and various high-performance interconnect protocols
• Experience in estimating and optimizing power consumption at the RTL level