RTL Engineer

자격 요건 · 5개

• Minimum 6+ years of combined experience in RTL design using SystemVerilog/Verilog (M.S. counted as 2 years, Ph.D. as 4 years toward this total). Fewer years with clear depth in interconnect or link-layer RTL is also worth a conversation.
• Block Ownership: you have owned at least one non-trivial block end to end in RTL. Prior architecture-definition experience is welcome but not required — you will define microarchitecture here with the architect beside you, not alone.
• Simulation & Debugging: proficiency in a logic simulation tool (VCS or Xcelium) with the ability to root-cause complex RTL issues.
• Quality Toolchain: familiarity with industry-standard quality flows — Lint, CDC, and Synthesis at minimum.
• Communication & collaboration: . strong, collaborative cross-functional work — root-causing a chiplet issue spans architecture, verification, firmware, PSI, and vendor teams, so we value engineers who debug with data rather than blame and own their mistakes honestly.

우대 사항 · 5개

• Tape-out & Silicon Bring-up: experience carrying a design through tape-out and into post-silicon debug. Valuable here, but not a requirement — the role includes bring-up, so you can also learn it on this project.
• Interconnect Protocols: working knowledge of AMBA (AXI/ACE) or CHI, or any packetized on-chip protocol — transaction ordering, outstanding-transaction management, and credit-based flow control.
• Clock, Reset & Low-Power Infrastructure: clock domain crossing, reset domain crossing, and power/clock gating in a multi-domain design.
• DFT: scan insertion, compression, and DFT-aware RTL practices.
• SerDes / high-speed PHY: working understanding of SerDes-based high-speed links — PCS/PMA partitioning, equalization, clock/data recovery, and link training — and the digital logic that interfaces to a SerDes PHY.