Low-Power Custom & Datapath Circuit Design: Deep expertise in ultra-low-power full-custom circuit design, including dynamic/domino logic, custom transistor-level circuit topologies, and non-standard CMOS logic structures.
Hands-on experience with latch-based timing methodology, pulse-latch design, and custom clock-tree/mesh optimization to minimize dynamic power and clock latency.
Datapath PPA & Circuit Optimization: Proven track record of designing high-efficiency datapath execution units (e.g., Adders, Multipliers, MACs, Register Files) using dynamic logic, low-swing signaling, and fine-grained power gating.
Experience in multi-VT and sub-threshold/near-threshold voltage design strategies to achieve industry-leading Performance-per-Watt.
Mass Production & Failure Analysis: Direct experience in High-Volume Manufacturing (HVM) support for mixed-signal IPs, including yield ramp-up, silicon failure analysis (FA), and root-cause debug.
Layout Coordination: Collaborate closely with layout engineers to optimize floorplanning, matching, and parasitic reduction.
Silicon Evaluation: Support the bring-up and characterization of silicon chips to validate IP performance against design specifications.
System Integration: Work with SoC integration teams to ensure seamless IP macro integration and top-level verification.
