Verification Strategy: Define and develop comprehensive verification plans for complex SoC Interconnects and Bus structures based on architectural specifications.
Testbench Development: Build and maintain advanced verification environments using UVM (Universal Verification Methodology) and SystemVerilog.
Protocol Validation: Verify high-speed bus protocols (AMBA AXI, CHI, ACE) to ensure data integrity, cache coherency, and protocol compliance.
Performance Verification: Analyze bus performance metrics including throughput, latency, and arbitration efficiency to identify and resolve bottlenecks.
Debug & Analysis: Conduct deep-dive debugging of complex RTL issues and perform code/functional coverage analysis to achieve 100% verification closure.
Gate-Level Simulation: Execute and verify GLS (Gate-Level Simulation) to ensure timing and functional correctness after synthesis.
