Subsystem Integration: Integrate ARM or RISC-V based CPU IP into AI SoC platforms, focusing on top-level connectivity and hierarchy.
Bus & Interconnect Design: Design and configure high-speed on-chip interconnects (NoC/NIC) using protocols such as AMBA (AXI, ACE, CHI) to ensure low-latency data paths.
Memory Hierarchy Management: Define and optimize the integration of L2/L3 caches, Snoop Control Units (SCU), and memory controllers.
Architecture Validation: Perform RTL-level integration checks, linting, and CDC (Clock Domain Crossing) analysis to ensure design integrity.
Performance Tuning: Collaborate with the Architecture team to analyze and resolve system bottlenecks related to CPU-to-NPU communication.
Cross-functional Collaboration: Work closely with Front-end/Back-end teams and Software/Firmware teams to define boot sequences and power management schemes.