Video Subsystem Integration: Integrate and configure 3rd-party Video Codec IPs to handle high-resolution video streams efficiently within the AI semiconductor architecture.
Display & Video Out Integration: Integrate Display Out Formatters, Video Out systems (e.g., HDMI Out, MIPI Out), and frame buffer compression IPs (specifically AFBC or AFRC) to deliver high-quality outputs while minimizing memory bandwidth and power consumption.
Video Data Flow Architecture: Design and implement the subsystem RTL to seamlessly connect video codecs, memory interfaces, and display pipelines, optimizing overall system throughput from rendering to final output.
Cross-functional Collaboration: Collaborate with hardware, software, and external IP vendor teams to resolve system-level bottlenecks and support the commercialization of edge AI devices.
